The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 16, 1999
Filed:
Oct. 28, 1997
Larry B Li, Plano, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
A clamping circuit (100) is provided for controlling an external switch, using a control signal, in response to monitoring a voltage at a first node. When the voltage at the first node exceeds a certain voltage, the clamping circuit (100) closes the external switch to complete a current path to reduce the voltage at the first node. The clamping circuit (100) includes a voltage divider circuit, a first device, a second device, a current mirror circuit, and a switch. The voltage divider circuit, which may be implemented using a resistor (30) and a resistor (32), is coupled between the first node and a fourth node and generates a divider voltage at a third node that is proportional to the voltage at the first node. The first device and the second device may be implemented using a first bipolar junction transistor (38) and a second bipolar junction transistor (40), respectively. The first device receives the divider voltage and generates a first current, and the second device receives the divider voltage and generates a second current in response. The current mirror circuit receives the first current and mirrors the first current to the second device where a reference signal is generated at a second node that corresponds to the initial difference between the first current and the second current. The current mirror device may be implemented using a FET (34) and a FET (36). The switch, which may be implemented as FET (50), receives the reference signal and provides the control signal to the external switch when the reference signal is received at an amplitude that exceeds a threshold level.