The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 16, 1999
Filed:
Jul. 01, 1997
Applicant:
Inventor:
Masayuki Ohashi, Tokyo, JP;
Assignee:
NEC Corporation, Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K / ;
U.S. Cl.
CPC ...
326104 ; 326121 ; 326119 ;
Abstract
An N-input transistor logic circuit includes two or four series-connected transistor arrays connected between two power lines. The gates of the transistors are connected to the N inputs to account for varying parasitic input capacitances, and equalizes the resulting time delays between the N-inputs and the logical unit output. Specifically, in each of the arrays each of the transistors is connected to one of the N inputs, and is separated from a first power line by X other transistors in the respective array. For each of the input terminals, the sum of X for all the arrays is a constant, namely, 2N-2 for four arrays and N-1 for two arrays.