The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 09, 1999

Filed:

Sep. 16, 1997
Applicant:
Inventors:

Franco Motika, Hopewell Junction, NY (US);

Stephen V Pateras, San Jose, CA (US);

John James Shushereba, Essex Junction, VT (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R / ;
U.S. Cl.
CPC ...
714733 ; 714 30 ;
Abstract

An integrated circuit comprising logic circuits and self-test circuits for testing logic circuits including a pseudo random pattern generator for generating at least one pseudo random pattern and weighing circuit for weighing the pseudo random pattern. The weighting circuit and pseudo random pattern generator generate a plurality of weighted pseudo random patterns including at least one pair of a first weighted pseudo random pattern and a second weighted pseudo random pattern that is the complement of the first pattern. A weighting instruction selects one of the first or second pseudo random patterns for testing the logic circuits.


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