The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 09, 1999

Filed:

Apr. 29, 1997
Applicant:
Inventors:

Takashi Higuchi, Tokyo, JP;

Naoto Okumura, Tokyo, JP;

Hideo Tsubota, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ; G06F / ; G11C / ; G11C / ;
U.S. Cl.
CPC ...
714 42 ; 714 28 ; 395527 ; 36518525 ; 365222 ; 36523003 ; 711106 ;
Abstract

A CPU can selectively execute a normal processing mode and a debugging mode on the basis of a control signal sent from a control unit. A first memory cell array is accessed in the normal processing mode, and a second memory cell array is accessed in the debugging mode. A sense amplifier and a bit line are shared by the first and second memory cell arrays. Consequently, it is possible to relieve an increase in the area of the semiconductor chip caused by existence of the two memory cell arrays. That is, an area of a semiconductor chip is reduced. A spare memory cell array may be provided for compensating for a defective cell of the first memory cell array. A refresh circuit may be provided for refreshing the first and second memory cell arrays.


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