The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 09, 1999

Filed:

Feb. 15, 1996
Applicant:
Inventors:

Daniel Frans Van de Pol, Brasschaat, BE;

Erik Moerman, Bottelare, BE;

Johan David, Leuven, BE;

Johannes Anthonius Van Tetering, Zevenbergen, NL;

Assignee:

Alcatel N.V., , NL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
714 31 ; 714712 ; 370509 ; 370510 ; 370512 ;
Abstract

To test the processing of a data frame processing unit (FPU) which, in a normal working mode, processes input data frames applied to a data frame input (FI) thereof, the data frame processing unit (FPU) is brought in a test mode. Therefore, an active test signal is applied to a test mode control input (TCI) of this data frame processing unit (FPU). When brought in the test mode, the frame counters of the data frame processing unit (FPU) have lower limits and test data frames with smaller dimensions than the input data frames applied to the data frame input (FI).


Find Patent Forward Citations

Van de Pol, Daniel. (1999). Frame processing unit with test mode, line termination module including (U.S. Patent No. 5983365). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5983365

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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