The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 09, 1999
Filed:
Jun. 18, 1996
Vimi Pandey, Santa Clara, CA (US);
Kenneth Ma, Cupertino, CA (US);
Leo Jiang, Fremont, CA (US);
Scott Shaw, Fremont, CA (US);
National Semiconductor Corporation, Santa Clara, CA (US);
Abstract
A method and apparatus is disclosed for controlling the application of a clock stopping signal in a processor to limit power consumption. The system controller receives addresses, signals indicative of primary and secondary system activity, and at least one nap timeout signal. Interrupt addresses or programmed addresses are trapped and stored as shadowed addresses. Current addresses may be compared with shadowed addresses. Matching addresses trigger a nap mode. Upon nap mode triggering, the clock stopping signal may be applied during a throttling period. Applying the clock stopping signal with programmable duty cycle during the throttling period ensures that processing necessary for the detection and servicing of primary and secondary activity can occur. A prefetch detect circuit ensures that shadowed addresses loaded in the middle of a prefetch do not trigger the clock stopping signal. Clock stopping signal is removed or inhibited when primary or secondary activity is detected or when a nap timer expires.