The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 09, 1999
Filed:
Sep. 26, 1997
Dennis Lee Wendell, Pleasanton, CA (US);
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Abstract
A power-up initialization circuit includes a transistor that generates a positive leakage current at the onset of a power-up ramp voltage. The positive leakage current drives a first node connected to a latch to a first defined state. The latch drives a complementary second node to a second defined state, complementary to the state of the first node. The latch acts as a keeper that is switchable and allows current flow during power-up but prevents leakage current when the power-up is complete and nodes are set to selected states. A keeper is a circuit element that holds a dynamic circuit to a static behavior. One type of keeper is a latch. Another type of keeper is a MOSFET transistor having a thin channel width and a gate terminal connected to a reference such as a ground or VSS reference. A power-up initialization circuit includes a capacitive switch connected to a power source and connected to a power-up control node, and a current source connected to the power source and connected to an internal node. The current source has a control terminal connected to the power-up control node. The current source sets a state at the internal node according to a signal on the power-up control node. The power-up initialization circuit furthers includes a latch connected to the internal node and connected to a controlled node. The latch sets a state of the controlled node opposite the state of the internal node.