Bus arrangements for interconnection of discrete and/or integrated

Abstract

Bus arrangements for interconnecting a number of discrete and/or integrated modules in a digital system are described herein. Implementations of the bus arrangements are contemplated at chip level, forming part of an overall integrated circuit, and are also contemplated as interconnecting discrete modules within an overall processing system. These bus arrangements and associated method provide for high speed, efficient digital data transfer between the modules through optimizing bus utilization by eliminating the need for maintaining a fixed time relationship between the address and data portions of transactions which are executed by the system. In this manner, the bus arrangement is capable of supporting more active transactions than the number of individual buses which make up the bus arrangement. Systems described may include any number of individual buses within their bus arrangements. In one implementation, a system includes a single address bus and two or more data buses such that different data transfers may be executed simultaneously on each data bus.