The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 09, 1999
Filed:
May. 12, 1997
Applicant:
Inventor:
Hemanth G Kanekal, San Jose, CA (US);
Assignee:
Cirrus Logic, Inc., Fremont, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
710110 ; 710100 ; 710107 ; 710113 ; 710129 ;
Abstract
A method and apparatus to prevent invalid data from propagating into devices connected to a PCI tristate bus is provided. The method and apparatus utilize the PCI bus control signals to monitor the bus transaction's mode (e.g., as a bus target or as a bus master), type (e.g., read, write), and status (e.g., ongoing bus transaction). Using these information, control the opening and closing of a window gate hardware to allow valid data to propagate into a device connected to the PCI tristate bus and to prevent invalid data from propagating into the device.