The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 09, 1999
Filed:
Jan. 20, 1998
Michael John Shay, Arlington, TX (US);
National Semiconductor Corp., Santa Clara, CA (US);
Abstract
A power management system pad clock and self-test circuit includes a clock processing circuit having a input configured to receive an oscillator clock signal having a first frequency. The clock processing circuit is configured to generate a first pad clock signal having a frequency approximately equal to one-half the first frequency and a second pad clock signal having a frequency that is equal to a programmable fraction of the first frequency. The circuit also includes a main pad clock output node. Multiplexer circuitry is coupled to the clock processing circuitry and the main pad clock output node and configured to receive a plurality of peripheral signals. The multiplexer circuitry is configured to operate in a standard mode of operation wherein one of the first pad clock signal and the second pad clock signal is routed to the main pad clock output node and a first test mode of operation wherein one of the plurality of peripheral signals is selectably routed to the main pad clock output node.