The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 09, 1999
Filed:
May. 30, 1997
Applicant:
Inventor:
Vishwani Deo Agrawal, New Providence, NJ (US);
Assignee:
Lucent Technologies Inc., Murray Hill, NJ (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
39550007 ; 39550003 ;
Abstract
The power dissipation in a circuit, e.g., a CMOS circuit, is reduced through hazard pulse suppression. More particularly, hazard-producing gates are those gates whose delays are smaller than the differential path delays for their inputs. The adjustment to the delay of these gates is made by increasing the gate delay as a function of the corresponding differential path delays to eliminate the production of hazard pulses. Thus, by suppressing the hazard pulses in a circuit the power dissipation of the circuit is substantially reduced.