Sense amplifier with improved bit line initialization

Abstract

A semiconductor memory includes cell array having a plurality of bit lines connected to respective input terminals of a column decoder. Input/output (I/O) lines are connected between respective output terminals of the column decoder and a plurality of sense circuits, where each sense circuit includes its own reference circuit, a sense amplifier, and equalizing circuit. The reference circuit includes a reference array essentially identical to the cell array and provides a reference voltage to respective first input terminals of its associated equalizing circuit and sense amplifier. Second input terminals of the equalizing circuit and sense amplifier of each sense circuit are connected to a corresponding I/O line. During read operations, the equalizing circuits are initially maintained in a conductive state so as to equalize the I/O line voltage and the reference voltages. Thereafter, the equalizing circuits transition to a non-conductive state so as to isolate the I/O line from the reference voltage. In response thereto, each I/O line voltage immediately changes to either a more positive or more negative voltage, depending on the binary state of the cell associated therewith.