The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 09, 1999
Filed:
Aug. 01, 1997
George McNeil Lattimore, Austin, TX (US);
Robert Anthony Ross, Jr, Cedar Park, TX (US);
Gus Wai-Yen Yeung, Austin, TX (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method and apparatus is provided for implementing a memory cell array having a performance-improved critical read path using a boost amplifier configuration. The memory bit line is broken into small segments with a boost amplifier and the bit line is connected to the input of the amplifier. The output of the amplifier drives the global bit line. The amplifier is turned 'on' during a 'read' and turned 'off' during a 'write'. During a read, one memory cell within one array segment is turned on. The memory cell drives the differential signal on to the local bit line pair. Also during a read, the boost amplifier which attaches to that local bit line is enabled. The boost amplifier amplifies the input signal (local bit line pair) and drives that signal on to the global bit line. Since the bit line is broken into small segments with boost amplifiers, there are many boost amplifiers attached on the global bit line. When enough signal is developed on the global bit line pair, the global sense amplifier is turned on. The bit line is thus quickly pulled to ground thereby significantly improving performance for the critical read path.