The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 09, 1999

Filed:

Feb. 10, 1999
Applicant:
Inventor:

Junya Kawamata, Kawasaki, JP;

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C / ;
U.S. Cl.
CPC ...
36518501 ; 36518511 ; 36518529 ; 365218 ;
Abstract

The present invention is a non-volatile memory comprising: first and second floating gate MOS transistors which are electrically written and erased and which are operatively connected between power sources serially; and an output terminal connected to the contact point of the first and second MOS transistors; wherein a first datum is stored by writing to the first MOS transistor and erasing the second MOS transistor, and a second datum is stored by erasing the first MOS transistor and writing to the second MOS transistor. With the aforementioned memory device, through current does not flow to the power source, because only one transistor will be conductive even if read voltage is applied to the control gate of both transistors. Consequently, reading time can be shortened, without leading to increased power consumption, by maintaining the control gate at the read voltage level.


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