The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 09, 1999
Filed:
Dec. 14, 1998
Paul McKay Moore, San Bruno, CA (US);
National Semiconductor Corporation, Santa Clara, CA (US);
Abstract
An array of pixel cells for a liquid crystal light value includes support pillars separating the array surface from a translucent top plate. During fabrication, a series of raised intersecting spacer walls having sides and a top surface are first formed by etching a thick oxide layer to stop on a nitride layer. Exposed nitride etch-stop layer is then removed, and electrode liner, metal electrode, and passivation layers are formed over the entire structure, including the sides and top surface of the spacer walls. Photoresist is then spun, hardened, and etched to expose the passivation formed over the tops of the spacer walls. The exposed passivation layer, and pixel liner and metal electrode material underneath the exposed passivation layer at the margins of the spacer walls are then etched. A photoresist mask is patterned to cover points of intersection of the spacer walls, and unmasked lengths of spacer walls are etched to stop on the nitride etch-stop layer. Stripping the photoresist mask reveals raised support pillars at the corners of the pixels, with pixel electrodes electrically isolated from each other by inter-pixel isolation strips formed by the nitride bases of the former spacer walls. Careful control of the prior etching along the spacer wall margins creates an array surface having electrodes substantially planar with the inter-pixel isolation strips.