Self-timed multiplier for gain compensation and reduced latency in

Abstract

A self-timed multiplier and method are disclosed together with an analog to digital converter (ADC), which reduces ADC latency without requiring large silicon areas for implementation. The self-timed multiplier may be utilized by delta-sigma ADCs to perform gain compensation multiplications at the end of convolution, or may be used by other ADC designs or ADC systems for multiplications required during each convolution. The self-timed multiplier utilizes cascaded adders that produce completion signals to isolate the operation of the self-timed multiplier from the system clock of the ADC. The multiplier disclosed provides a self-timed, asynchronous circuit that will complete the desired multiplication in the time it takes for the required additions to propagate through the cascaded adders. This propagation time preferably falls within a single system clock cycle of the ADC, and the self-timed multiplier disclosed is particularly advantageous for ADCs with relatively slow system clock speeds for which a multiplication may be completed within a single system clock cycle. The self-timed multiplier may also be made data dependent to save power and to reduce the time required for the additions to propagate through the cascaded adders.