Static random access memory cell having buried sidewall transistors,

Abstract

A static random access memory (SRAM) cell has a decreased cell size and utilizes transistors disposed in a number of trenches. Four trenches generally contain six transistors associated with the memory cell. The transistors are provided as sidewall transistors which are coupled to buried bit lines, VSS nodes, and VDD nodes at the bottom of the trenches. A first trench includes a driver transistor and a load transistor which have gates coupled together by a bridge over the trench. Another bridge is provided over the bridge over the trench to couple the source of the load transistor to the drain of the driver transistor. The drain of the driver transistor is coupled to another drain of the access gate transistor. The access gate transistor is located in a trench with a access gate transistor from another cell. The buried bit line is located in the trench with the access gate transistors.