The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 09, 1999
Filed:
Dec. 08, 1997
Ian D French, Hove, GB;
Martin J Powell, Horley, GB;
U.S. Philips Corporation, New York, NY (US);
Abstract
In the manufacture of a flat panel display or other large-area electronics device, a self-aligned thin-film transistor (TFT) is formed with source and drain silicide parts (31,32) adjacent an insulated gate structure (25,21,22) on a silicon film (20) which provides a transistor body (20a) comprising a channel area (20b) of the transistor. The transistor has its source and drain electrode pattern (11,12) extending under the silicon film (20). The insulated gate structure (25,21,22) is formed as a conductive gate (25) on an insulating film (21,22) which is patterned together with the conductive gate (25). A silicide-forming metal (30) is deposited over the insulated gate structure (25,21,22) and over exposed, adjacent areas (20c and 20d) of the silicon film, and the metal is reacted to form the silicide (31,32) with these adjacent areas of the silicon film. The unreacted metal is removed from the insulated gate structure (25,21,22) by means of a selective etchant to leave the source and drain silicide parts (31 and 32) self-aligned with the conductive gate (25). An electrical connection (n+; 31,32) is formed across the thickness of the silicon film (20) between the source and drain electrode pattern (11,12) and the respective source and drain silicide parts (31 and 32).