The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 02, 1999
Filed:
Jun. 30, 1997
Toshiki Narukawa, Kasugai, JP;
Brother Kogyo Kabushiki Kaisha, Nagoya, JP;
Abstract
A semiconductor integrated circuit enables an easy check of operations in a user logic section or of internal malfunction. A controller in an application specified integrated circuit (ASIC) includes a CPU, RAM, ROM and a user logic section which are mutually connected to one another. The ROM is connected to the user logic section through a first bus control circuit, and the RAM and CPU are connected thereto through a second bus control circuit. The first bus control circuit disconnects the ROM from the user logic section in accordance with a selection signal SA, and the second bus control circuit disconnects the RAM and CPU 16 from the user logic section in accordance with a mode selection signal SA1. Thus, three modes can be selectively set, which include a normal mode in which none of the CPU, RAM and ROM is disconnected, an external ROM mode in which only the ROM is disconnected, and an external CPU mode in which the ROM, RAM and CPU are disconnected. When the external CPU mode is set, the operational check of the user logic section can be performed.