System for performing dma transfers where an interrupt request signal is

Abstract

A microcontroller is presented which is configurable to transfer data to and from one or more asynchronous serial ports (ASPs) using direct memory access (DMA), and having hardware features which cause each ASP to notify the microprocessor core (i.e., execution unit) when a data frame having a last data bit equal to a predetermined value is received. Such hardware features allow the execution unit to determine when complete data packets are received. Each ASP is adapted to receive serial communication data, and is configurable to generate an internal DMA request signal in response to the serial communication data. The serial communication data is transmitted within data frames, wherein each data frame includes multiple data bits transmitted sequentially between a start bit and one or more stop bits. The last data bit of the multiple data bits is transmitted immediately before the one or more stop bits. Each ASP is configurable to generate an ASP interrupt request signal when the value of the last of the multiple data bits is equal to a predetermined value, preferably when the last data bit is set to 1 as commonly used to signal the beginning or end of a data packet. Each ASP includes at least one configuration register, the contents of which determine the operation of the ASP. Generation of the ASP interrupt request signal and the internal DMA request signal is determined by the contents of at least one bit position within the configuration register.