Low power video decoder system with block-based motion compensation

Abstract

A battery-powered computing system (20) including video decoding capability, particularly as pertinent to the H.263 standard, is disclosed. The system (20) includes a main integrated circuit (30) having an on-chip central processing unit (CPU) (32) and on-chip shared memory (33) for the temporary buffering of video image data that is retrieved and generated during the video decoding process. The CPU (32) is programmed to perform a combined P and B prediction process (46) upon a previously predicted P frame (P.sub.T-1), with accesses to internal buffers in shared memory (33) instead of to main memory (40). Preferably, inverse transform processes (48, 52) also access shared memory (33) rather than main memory (40). The combined P and B prediction process (46) preferably handles unrestricted motion vectors using edge pixels (P.sub.edge) stored in an edge buffer (44e) in the on-chip memory (33), by modifying (58, 60) motion vector components (MVx, MVy) that point outside of the displayable video image, and retrieving the corresponding edge pixels (P.sub.edge) from the edge buffer (44e) in this event. The on-chip memory (33) preferably also includes a buffer (NEWBFR) for storing current predicted P blocks, such that the previous predicted P frame (P.sub.T-1) and the current predicted P frame (P.sub.T) can share the same memory space (old/newframe). The power requirements of the video decoding process are thus much reduced, as memory accesses to large, off-chip, main memory (40) are limited.