Binary counter system using bit-wise matches with maximum count

Abstract

A counting system with a dynamic maximum count includes a counter, match logic, and a maximum count controller. The counter has a present count register, a clock (or event indicator) event input, and a reset input. The maximum count controller can be programmed with an adjustable maximum count stored in a maximum count register. The match logic includes a count-wide AND gate fed by NAND gates. Each NAND gate has an inverted input coupled to a respective bit position of the present count register and an uninverted input coupled to a respective bit position of the maximum count register. The function of the match logic is to indicate a match whenever the present count has a 1 at every bit position that the maximum count has a 1, irrespective of the present count values at bit positions at which the maximum count has 0s. Thus, imperfect matches are provided for. The values of the imperfect matches always exceed the values of perfect matches, so they are not usually encountered. However, in the case the maximum count is adjusted from above to below the present count, the invention achieves the desired change in rate of match indications more quickly than would be achieved if perfect matches were required. In addition, the match logic for the imperfect matches is simpler than the logic required for perfect matches. Thus, the invention provides both better functionality and a simpler implementation of a counting system.