The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 02, 1999
Filed:
Aug. 22, 1997
Shigeru Kuhara, Tokyo, JP;
NEC Corporation, Tokyo, JP;
Abstract
A PLL circuit detects a locked state as keeping always constant the ratio of an input signal to a locked state detection reference value by automatically and continuously changing the locked state detection reference value even when the frequency of the input signal is changed. A division ratio of a frequency divider in the PLL circuit is changed in response to an external signal. An analog signal Vc which is output from a loop filter 3 is applied to a delay circuit 7. When the analog signal Vc rises, a delay time Td of the delay circuit 7 decreases. The locked state detection reference value varies according to the frequency of the signal f1.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile