Integrated circuit memory devices having partitioned multi-port memory

Abstract

Multi-port memory arrays having partitioned registers therein are provided. The registers are partitioned into subarrays so that at least two columns of a selected register can be simultaneously written to (or read from) using first and second input/output driver circuits. These first and second input/output driver circuits are electrically coupled to respective read and write data ports at opposing ends of the memory array. Control logic and first and second input/output driver circuits are provided for writing a first portion of a word of data into a first subarray while simultaneously writing a second portion of the word of data into a second subarray. Here, the first and second portions may comprise the least significant and most significant bytes of the word of data. The first input/output driver circuit is also electrically coupled to first read and write data lines at a first end of the memory array and the second input/output driver circuit is electrically coupled to second read and write data lines at a second end of the memory array. A data flow control circuit containing a crosspoint switch is also provided for routing input and output data between input and output registers and the first and second input/output driver circuits. The data flow control circuit, preferred arrangement of memory cells and dual input/output driver circuits also enables 2.times., 1.times. and 1/2.times. word width capability which can be selected by a user, for example.