The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 02, 1999

Filed:

Jan. 04, 1999
Applicant:
Inventors:

Darren L Anand, Essex Junction, VT (US);

Robert Tamlyn, Jericho, VT (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C / ;
U.S. Cl.
CPC ...
36518905 ; 365233 ; 3652335 ;
Abstract

A postamble corruption protection circuit is provided that disables data latching by a first falling edge register following a data strobe (DQS) falling edge until the data within the first falling edge register has been latched into a second falling edge register in response to a second falling edge register latching signal. Specifically, data latching by the first falling edge register is disabled following each DQS falling edge and is enabled following each second falling edge register latching signal. Data latching of the first falling edge register is controlled by the output of a set/reset register which is gated with the DQS to form a first falling edge register latching signal. When the set/reset register is set, data latching is enabled and when the set/reset register is reset, data latching is disabled. The set/reset register is set in response to a second falling edge register latching signal and is reset in response to a DQS falling edge.


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