The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 02, 1999
Filed:
Feb. 17, 1998
Applicant:
Inventors:
Pau-ling Chen, Saratoga, CA (US);
Shane C Hollmer, San Jose, CA (US);
Binh Q Le, Mountain View, CA (US);
Michael S Chung, San Jose, CA (US);
Assignee:
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C / ;
U.S. Cl.
CPC ...
36518517 ; 36518502 ; 36518528 ;
Abstract
A method is provided for biasing a NAND array EEPROM during programming to allow the array to be scaled down further before reach punchthrough. The sources of the ground-select transistors of the NAND array are biased at V.sub.cc instead of ground to reduce the voltage drop across the source and drain of the ground-select transistors. As a result, the channel length of the ground-select transistors can be further shortened before punchthrough is obtained, resulting in a higher density EEPROM.