Semiconductor memory device stably storing multiple-valued data without

Abstract

A semiconductor dynamic random access memory device has memory cells each storing a piece of multiple-valued data equivalent to two-bit binary data in the form of electric charge, and sub-bit line pairs selectively connected to the memory cells use parasitic capacitors coupled thereto as charge accumulators weighted by two, wherein the piece of multiple-valued data transferred from the sub-bit line pair to a main bit line pair supplies a first potential level to one of the charge accumulators assigned to the most significant bit and a second potential level to another of the charge accumulators assigned to the least significant bit, and dummy cells are selectively coupled to the charge accumulators so as to make storage capacitance coupled to the charge accumulator assigned to the most significant bit twice as large as the storage capacitance coupled to the charge accumulator assigned to the least significant bit, thereby eliminating electrical influence of the storage capacitor of the selected memory cell from a restore level.