The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 02, 1999

Filed:

May. 16, 1996
Applicant:
Inventors:

Yuichi Nakatani, Sendai, JP;

Satoshi Takahashi, Sendai, JP;

Masami Aiura, Sendai, JP;

Assignee:

Motorola, Inc., Schaumburg, IL (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03M / ;
U.S. Cl.
CPC ...
341118 ; 327391 ; 327437 ;
Abstract

An offset cancellation circuit(1) for an analog switch(10) is provided which substantially reduces the offset voltage induced by the analog switch circuit. The circuit(1) comprising a second P-channel transistor(2) and a third N-channel transistor(4) connected to each other in series, the drains of the second P-channel transistor and the third N-channel transistor being connected to the output terminal; a second N-channel transistor(3) and a third P-channel transistor(5) connected to each other in series, the drains of the second N-channel transistor and the third P-channel transistor being connected to the output terminal; the gate of the second P-channel transistor is connected to the gate of the N-channel transistor; and the gate of the second N-channel transistor is connected to the gate of the P-channel transistor.


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