The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 02, 1999

Filed:

Mar. 25, 1998
Applicant:
Inventors:

Yasushi Sogabe, Tokyo, JP;

Fumio Ishizu, Tokyo, JP;

Keishi Murakami, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03D / ; H04L / ; H04L / ;
U.S. Cl.
CPC ...
329306 ; 329310 ; 375329 ; 375324 ;
Abstract

The presence or absence of a clock component is detected for an input signal. If the input signal does not comprise a clock component, the operation of a computing circuit is halted, thereby further improving the accuracy of phase estimation. A signal generating circuit produces a twiddle factor for DFT. A DFT circuit performs discrete Fourier transform on an input signal for a predetermined number of symbols based on the twiddle factor for DFT. A pattern detecting circuit examines the input signal for its pattern based on the output from the DFT circuit. An averaging filter turns on or off the operation of the subsequent averaging filter according to the detected pattern, and averages the outputs from the DFT circuit to remove a noise component.


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