The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 02, 1999
Filed:
Oct. 20, 1997
Kamran Iravani, San Jose, CA (US);
VLSI Technology, Inc., San Jose, CA (US);
Abstract
The differential MOS current-mode logic structure of the present invention is comprised of a differential MOS transistor pair and a complementary MOS (CMOS) transistor for each of the transistors comprising the differential MOS pair. The gates of the CMOS transistors are coupled to the gates of the differential MOS pair. Since the gates of the differential MOS pair receive a differential signal from the inputs, the voltage between the gate and the source, Vgs, for each of the transistors comprising the MOS differential pair is not fixed. As a result, the gain of the CMOS current-mode logic structure of the present invention is high. In addition, since the gates of the CMOS transistors are coupled to the gates of the differential MOS pair, the current for the CMOS transistors is increased when charging the node capacitance and is decreased when discharging the node capacitance. Hence, the present invention allows faster charging and discharging of transistors, which results in faster switching transistors and higher speed circuit.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile