Layout structure of semiconductor memory with cells positioned in

Abstract

A layout structure of an SRAM for reductions in the number of interconnect layers and in the number of connection holes with conventional advantages maintained is disclosed. Contact holes and fields which have been shared between cells vertically adjacent to each other in plan view are divided between the cells. The cells are then positioned in translated relation also in a bit line direction (D1). In a resultant region, first-level polysilicon interconnect layers (1G(G)) for a GND line and first-level polysilicon interconnect layers (1G(W)) for a word line are formed in parallel in a word line direction (D2). Connection holes (GK2, GK1) for connecting gate electrodes of driver transistors (DTr1, DTr2) and fields (FL) are also used for connection holes (GK3) for connecting the fields (FL) and the GND interconnect layers (1G(G)). Further, interconnect layers having a high power supply potential is formed on the interconnect layers (1G(G)).