The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 02, 1999

Filed:

Aug. 01, 1996
Applicant:
Inventors:

Junko Matsubara, Hyogo, JP;

Toru Tajima, Hyogo, JP;

Shigeru Harada, Hyogo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
B05D / ;
U.S. Cl.
CPC ...
427307 ; 428195 ; 427309 ; 501 92 ; 438769 ; 438782 ; 438787 ; 438788 ;
Abstract

A method of manufacturing a semiconductor device is provided superior in planarization, crack resistance, and moisture resistance, and with no corrosion in wiring while the manufacturing cost is suppressed without increasing the number of manufacturing steps in forming an interlayer film therein. This method includes the step of forming a silicon oxide film on a substrate so as to cover a first wiring formed with a silicon oxide film therebetween. A thick-film inorganic SOG film is coated on the silicon oxide film, and then a thermal treatment is applied. Next, a silicon oxide film is formed, and a via hole is formed according to a predetermined mask. By carrying out a thermal treatment at the temperature of 150.about.550.degree. C. and at the pressure of not more than 10.sup.-3 Torr with a portion of the thick-film inorganic SOG film exposed at a side surface of the via hole, residual gas such as CO.sub.2, and H.sub.2 O adsorbed to the side surface of the via hole is released. Thus, corrosion of a wiring that is subsequently formed will be prevented to obtain a semiconductor device of high reliability.


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