The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 26, 1999
Filed:
Jan. 05, 1998
John J Wang, San Jose, CA (US);
Yuesong He, San Jose, CA (US);
Kent Kuohua Chang, Cupertino, CA (US);
Advanced Micro Devices, Inc., Sunnyval, CA (US);
Abstract
A method and apparatus for an integrated circuit on a semiconductor substrate having good metal contact points. A first polysilicon layer is formed onto the substrate, and is etched to provide contact regions to the substrate. An ONO layer is formed onto the first polysilicon layer. A second polysilicon layer is formed onto the ONO layer, and a metal silicide layer is formed onto the second polysilicon layer. The second polysilicon layer and the metal silicide layer are etched at particular locations in order to form contact regions to the first polysilicon layer and to the substrate. A selective layer is formed onto the second polysilicon layer, the selective layer being etch selective with respect to the first polysilicon layer. An interlayer dielectric is formed onto the selective layer. A first etching is performed to provide a contact path through the interlayer dielectric, and then a second etching is performed to provide a contact path through the selective layer. Based on these two contact paths, a contact point can be provided externally to the first polysilicon layer.