The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 19, 1999
Filed:
Mar. 27, 1996
Armand Pruijmboom, Albuquerque, NM (US);
Alexander C Jansen, Nijmegen, NL;
Ronald Koster, Eindhoven, NL;
Willem Van Der Wel, Nijmegen, NL;
U.S. Philips Corporation, New York, NY (US);
Abstract
A method of manufacturing a semiconductor device with a bipolar transistor (1) and a MOS transistor (2) formed in a silicon body (3) which for this purpose is provided with a field insulation region (4) by which semiconductor regions (6, 7) adjoining a surface (5) of said body are mutually insulated. A first region (6) is destined for the bipolar transistor and a second region (7) for the MOS transistor. The second region is provided with a gate dielectric (10). Then an electrode layer of non-crystalline silicon (11) is provided on the surface, which electrode layer is provided with a doping and in which electrode layer subsequently an emitter electrode (12) is formed on the first region and a gate electrode (13) on the second region. The electrode layer is provided with a doping by means of a treatment whereby a first dopant is provided at the area of the first region and a second dopant at the area of the second region, the first dopant being provided to a concentration such that the emitter zone of the transistor can be formed through diffusion from the emitter electrode to be formed in the electrode layer, while the second dopant is provided to a concentration lower than that of the first dopant. Owing to the comparatively low doping level, gate oxide breakdown is prevented during plasma etching and ion implantation.