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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 5970001 B1

PDFFull Text
Date of Patent:
Oct. 19, 1999

Filed:

Mar. 05, 1998

Dynamic ram provided with a defect relief circuit

Applicant:
Inventors:

Hiromasa Noda, Tokyo, JP;

Kenji Nishimoto, Urawa, JP;

Yoshitaka Kinoshita, Akishima, JP;

Masakazu Aoki, Tokorozawa, JP;

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorney:

Antonelli, Terry, Stout & Kraus, LLP

Primary Examiner:

David Nelms

Assistant Examiner:

M Tran

Int. Cl.
CPC ...
G11C / ;
U.S. Cl.
CPC ...
365200 ; 36518907 ;
Abstract

An X address buffer for generating an internal address signal by capturing an X address signal input from an address terminal is brought into an operating state before an external control clock is input. A redundancy address comparator for detecting a match/mismatch signal by comparing the generated internal address signal with a stored X-system defective address is used as a static circuit. Thereby, the redundancy address comparator starting operation is accelerated and as a result, acceleration of the reading operation is achieved.

Find Patent Forward Citations

Noda, Hiromasa. (1999). Dynamic ram provided with a defect relief circuit (U.S. Patent No. 5970001). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5970001

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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