Merged memory logic integrated circuits including buffers driven by

Abstract

A merged memory logic (MML) integrated circuit includes an adjustable clock generator configured to receive a input clock signal and produce an adjustably delayed clock signal therefrom responsively to a control signal generated by a programmable logic circuit. A buffer has a clock input for receiving the adjustably delayed clock signal and is configured to receive an input data signal and produce a corresponding output data signal therefrom responsive to the adjustably delayed clock signal. The adjustable clock generator preferably includes a clock generator configured to receive the input clock signal and produce a output clock signal therefrom, and an adjustable delay circuit which receives the output clock signal and generates the adjustably delayed clock signal therefrom, the adjustably delayed clock signal being delayed by a selected one of a plurality of selectable delay intervals with respect to the output clock signal. The adjustable delay circuit may include a plurality of delay circuits, a respective one of which is configured to receive the output clock signal and produce a respective delayed clock signal therefrom, the delayed clock signal being delayed a respective predetermined delay with respect to the output clock signal. One of the delayed clock signals is selectively coupled to the clock input of the buffer, preferably through a switch of a plurality of switches which are operative to connect the plurality of delay circuits to the clock input of the buffer.