Abnormal clock signal detector and switching device

Abstract

A system clock signal switching device capable of switching outputs from a plurality of clock signal generation systems i order to ensure the continuous supply of a stable system clock signal. An oscillation circuit A generates a clock signal CK1 as an ordinary system clock signal while an oscillation circuit B generates a clock signal CK2 as another separate clock signal, such as the time-count clock signal. The output lines of these circuits are connected with the input terminals of a multiplexer. An output clock signal monitor circuit checks the clock signal CK1 from the oscillation circuit A, wherein input terminals of the monitor are connected with the output lines to attain the operational clock signals for its monitoring operation. A monitor flag from the monitor circuit is supplied to a switching signal input terminal of the multiplexer via a line. An output line of the multiplexer is provided to a subsequent circuit using the system clock signal while the output line of the oscillation circuit B is provided to the subsequent circuits such as a time-count circuit.