Data transfer device for decreasing load of cpu by avoiding direct

Abstract

A data transfer controller connected between a device and a memory for controlling data transfer between the device and memory on the basis of a command received from a CPU. The controller includes command buffers for storing at least one data transfer command received from the CPU, an input port for reading the data transfer command from the command buffers and reading out a command packet corresponding to the data transfer command from a location within the memory instructed by the data transfer command, a packet store buffer connected to the input port for holding therein data packets and command packet read out from the memory, and a command execution circuit connected to the command buffers and the packet sore buffer for performing transfer of the data packets between the memory and device through the packet store buffer on the basis of a transfer execution flag received from the CPU. At least one data transfer command has a write command for transferring data from the memory to the device, and a read command for transferring data from the device to the memory, and the command execution circuit sends the data packets sent from the device to the packet store buffer on the basis of the data transfer command, according to a designation of the read command. When the data packet designated to be sent from the device to the packet store buffer according to the data transfer command is not held yet in the packet store buffer, the read command may not be executed. Two computer systems can be interconnected by means of respective data transfer devices to a parallel computer system as a whole.