Multiplexing dram control signals and chip select on a processor

Abstract

A DRAM controller is incorporated onto an existing microcontroller architecture. Existing chip select signals or other signals on the microcontroller are multiplexed with RAS and CAS signals. The RAS and CAS signals are asserted when an address is within a specific programmable address range and DRAM mode is enabled. The pins selected for RAS and CAS provide regular signals such as chip selects when not in DRAM mode. The timing of the chip select signal signals are adjusted when the chip select signals are utilized as column and row address strobes. Additionally, multiplexed addresses are provided from the microcontroller as well as refresh control. The microcontroller can provide high byte and low byte access by providing an upper column address strobe signal (UCAS) to support access for high byte and word access and a lower column address strobe signal (LCAS) to support low byte and word access. Mid range chip selects provide the UCAS and LCAS signals. A lower chip select signal (LCS) may provide a first RAS signal which is active in a first DRAM mode. The LCS signal is asserted as a first RAS signal when an address within a programmable memory range and the first DRAM mode is enabled. A second RAS signal provides access to a DRAM mapped into the upper half of memory. A mid range chip select pin is multiplexed with the second RAS signal.