Structure and method for instruction boundary machine state restoration

Abstract

A high-performance processor is disclosed with structure and methods for: (1) aggressively scheduling long latency instructions including load/store instructions while maintaining precise state; (2) maintaining and restoring state at any instruction boundary; (3) tracking instruction status; (4) checkpointing instructions; (5) creating, maintaining, and using a time-out checkpoint; (6) tracking floating-point exceptions; (7) creating, maintaining, and using a watchpoint for plural, simultaneous, unresolved-branch evaluation; and (9) increasing processor throughput while maintaining precise state. In one embodiment of the invention, a method of restoring machine state in a processor at any instruction boundary is disclosed. For any instruction which may modify control registers, the processor is either synchronized prior to execution or an instruction checkpoint is stored to preserve state; and for any instruction that creates a program counter discontinuity an instruction checkpoint is stored. Instruction execution status is monitored to detect a fault condition and if a fault occurs, the instruction identifier is saved according to predetermined rules and used as an endpoint to backup the program counter. If the faulting instruction is a checkpointed instruction, then the state information is restored from the checkpoint prior to reexecuting the faulting instruction, but if one of the instructions for which state was stored is sequentially between the faulting instruction and the last issued instruction, then (i) backing-up said processor to the closest checkpoint after the faulting instruction, (ii) back stepping the processor to restore state, and (iii) decrementing the program counter to the faulting instruction.