Semiconductor memory device

Abstract

A semiconductor memory device includes normal row selection lines (NWL1 to NWL128) for selecting one of normal rows, a spare row selection line (SWL) for selecting a spare row instead when one of the normal rows has a defect, fuses (F1 to F128) which are respectively arranged on the normal row selection lines, and blown when a defect exists, a normal row non-selection circuit (inverters IN3 and IN6 and gate G3) when one of the fuses (F1 to F128) is blown, setting a corresponding normal row in a non-selected state, and a spare row selection circuit (gates G4, G5, and G6, transistors P2 and N1, a NOR gate NR1, and an inverter IN6) selecting the spare row instead of the defective normal row. The spare row selection circuit performs dynamic operation in synchronism with a clock (ck). In this manner, control of, when a defect exists in a normal row or column, switching the defective row or column to a spare row or column is performed by dynamic operation in synchronism with an internal clock, thereby increasing the access speed.