Semiconductor memory device composed of half cells

Abstract

The disclosed semiconductor memory cell can be formed in accordance with the standard process for the logic LSI, so that the manufacturing cost can be reduced and an increased node capacitance can be secured. The drain diffusion layer (D1) of the latch transistor (M1) for constituting the latch of the memory cell is connected to a portion in the first metal layer through the contact (C1); the source diffusion layer (S1) of the latch transistor (M1) is the grounded wire connected to the first metal layer wire through the contacts (C3 and C3a); the poly silicon (P1) of the latch transistor (M1) is connected to the first metal layer wire or the second metal layer wire through the contact (C2); the first metal layer and the second metal layer are connected to each other by the through hole (V1) formed being overlapped with the contact (C3); the gate of the select transistor (M2) having the source connected to the drain diffusion layer (D1) of the latch transistor (M1) is connected to the word line (WL) of the poly silicon layer; the drain of the select transistor (M2) is connected to the first metal layer wiring through the contact (C4) and further connected to the bit lines formed in the second metal layer through the through hole (V2).