Method for automating top-down design processing for the design of lsi

Abstract

A netlist between functional macros is entered. Based on the netlist, an outline layout process for a functional macro is performed and physical specifications for the functional macro are determined from an outline layout produced by the outline layout process. Thereafter, a logic synthesis process is performed on the basis of the physical specifications determined. Based on the outline layout, a logic, obtained by the logic synthesis, is laid out. This makes it possible to reduce the number of times a circuit synthesis process is redone, taking into account a laying-out at an upper-stage functional design process in which no gate level is specified. For this reason, an improved LSI automatic design method is provided which is able to complete an LSI layout design, in which the LSI area and the LSI delay value are optimized, in a short period of time.