The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 05, 1999
Filed:
Jun. 26, 1997
Sandeep A Aji, San Francisco, CA (US);
Manjunath Doreswamy, Sunnyvale, CA (US);
Georgios Konstadinidis, Sunnyvale, CA (US);
Sun Microsystems Inc., Palo Alto, CA (US);
Abstract
An automated method detects electromigration violations in an integrated circuit design. Starting from the lowest hierarchy of the design so far completed, the parasitic (resistance and capacitance) component values extracted from a layout file are propagated up. Then, at the top-most level, lumping algorithms are employed to calculate the parasitic values for all of the top-most level nets. These values are then passed back down to the lower levels and then at each level, the layout is checked using previously computed parasitic values and EM limits. A peak current, AC-average current and AC-rms current are calculated for every layout, and then compared with the process EM rules for violations, in which the optimum line width and number of vias are specified for each interconnection.