Semiconductor memory having bitline precharge circuit

Abstract

A semiconductor device is provided having a symmetric bitline precharge circuit. Sizes of a parasitic devices near transistors lying symmetrically in the bitline precharge circuit are symmetrical to each other. Further, a layout area occupied by the bitline precharge circuit or a chip is reduced or minimized by the symmetric layout. The device can include a memory having first and second bitline extending in parallel a first direction a bitline precharge voltage supplying line and a bitline equalizing signal line extending in parallel in a second direction perpendicular to the first direction. A gate has at least a first part extending in the first direction, a second part having a first predetermined length extending in the second direction coupled to the first part and a third part having a second predetermined length extending in the second direction coupled to the first part with contact areas at uncoupled ends. An active region is on portions of the first and second bitline, the bitline precharge voltage supplying line, the first part and the second part of the gate. A first contact located between the first and second bitline to electrically couples the bitline precharge voltage supplying line and the active region. Second and third contacts electrically couple the gate to the bitline equalizing signal line, and fourth and firth contacts electrically couple the first and the second bitlines to the active region.