Undershoot hardened fet switch

Abstract

A bus switch for transferring logic signals between nodes without the problems associated with undershoot conduction. The bus switch is an FET switch including a single primary transfer transistor. The bulk of the transfer transistor is coupled to a bulk regulating circuit including a pseudo low-potential power rail. The pseudo low-potential rail is coupled to one arbiter circuit associated with one of the two circuit transfer nodes and a second arbiter circuit associated with the other of the two transfer nodes. The arbiter circuits are coupled to their respective nodes or pads and to a common low-potential supply rail. The arbiter selects for coupling to the pseudo low-potential rail the signal of the lower potential between that at the pad and that of the low-potential rail. This arrangement ensures that there will be no parasitic conduction of the transfer transistor during undershoot conditions. In an alternative embodiment that may be used to minimize the vagaries associated with process variations, the transfer transistor's gate may be independently coupled to a second pseudo low-potential power rail.