The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 05, 1999
Filed:
Apr. 14, 1997
Joseph Shor, Raanana, IL;
Mark Yosefin, Beit Hakerem Jerusalem, IL;
Dan Mauricio Bruck, Rishon Le Zion, IL;
Motorola, Inc., Schaumburg, IL (US);
Abstract
In a circuit (10), a first N-FET (N1) and a second N-FET (N2) are coupled serially between a node (15) and ground (93). The circuit (10) accommodates a first excursion (85) of a first signal (IN) at the gates of the first N-FET (N1) which is higher than the maximum allowable drain-source voltage for N-FETs. The voltage of a second signal (OUT) between the node (15) and ground (93) is distributed across the first and the second N-FETs (N1, N2). The gate voltage of the second N-FET (N2) is not constant, but controlled by a control circuit (20) receiving signals the first signal (IN) and, optionally, the second signal (OUT). With the variation of the gate voltage for the second N-FET (N2), the size of both transistors (N1, N2) can be reduced and the fall time (T.sub.F) of the second signal (OUT) can be reduced.