The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 05, 1999
Filed:
Jan. 22, 1998
Ahmad Dowlatabadi, San Jose, CA (US);
Nanoamp Solutions, Inc., San Jose, CA (US);
Abstract
An adjustable duty-cycle circuit includes an EXCLUSIVE-OR circuit for combining a divided reference input signal at a frequency .function..sub.IN /2 with a variably delayed divided reference input signal to provide an output frequency V.sub.O at .function..sub.IN with an adjustable duty cycle. A variable delay circuit, or delay line, is controlled by a control signal which is generated by comparing a signal equal to the average (DC) value of V.sub.O with an adjustable DC reference signal from a voltage divider or a DAC. An output signal from the comparator is filtered to provide the control signal V.sub.C for the delay circuit to control the duty cycle of the output signal. To provide a frequency doubler, the reference input signal is not divided by two to thereby obtain an output signal at 2.function..sub.IN with an adjustable duty cycle. Frequency multipliers for N=3, 5, 7, etc. are implemented with additional delays and exclusive logic circuits.