Power surge management for high performance integrated circuit

Abstract

An integrated circuit chip configuration, e.g., a microprocessor, includes feedback control circuitry defined thereon to control mid-frequency components of current demand of the integrated circuit chip and thereby regulate power supply voltage to within design tolerances of the integrated circuit chip. Such mid-frequency components can be generated by directed changes in operating frequency of the integrated circuit chip or by cyclic or episodic variations in circuit activity, e.g., instruction sequence dependent variations. When generated, such mid-frequency components can excite mid-frequency resonances in a power distribution system and generate power supply voltage disturbances. In some configurations, the integrated circuit chip includes current dump circuitry defining a controlled impedance path between first and second power supply voltage terminals of the integrated circuit chip. The controlled impedance path allows the feedback control circuitry to actuate a variable current draw so as to reduce mid-frequency components of overall current demand of the integrated circuit chip and thereby regulate power supply voltage disturbances. In other configurations, the feedback control circuitry is coupled to on-chip clock circuits, e.g., a phase-locked loop (PLL), to actuate variations in a clock signal supplied to the integrated circuit chip and thereby regulate power supply voltage disturbances.