The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 05, 1999
Filed:
Apr. 11, 1997
George L Kerber, San Diego, CA (US);
Lynn A Abelson, Rancho Palos Verdes, CA (US);
Raffi N Elmadjian, Arcadia, CA (US);
Eric G Ladizinsky, Canoga Park, CA (US);
TRW Inc., Redondo Beach, CA (US);
Abstract
A high-temperature (10 K) superconductive integrated circuit has a ground plane (2), an interlevel dielectric (6), and a low value resistor (18) to provide conductive paths to reduce parasitic circuit inductances, thereby increasing the speed and performance of the integrated circuit. The circuit also includes a high value resistor (20) connected between interconnect wires (34) to produce a desired resistance with a short distance between the interconnect wires (34), thereby significantly reducing the circuit area. A method of fabricating the integrated circuit includes depositing the interlevel dielectric (6) on the ground plane (2) in separate steps, depositing and etching the trilayer (12, 14, 16), etching the low value resistor (18) on the dielectric (6), depositing the high value resistor (20) at substantially the same level above the ground plane (2) as the interconnect wires (22) of the first wire layer (24), and etching the interconnect wires (34) of the second wire layer (32) on the high value resistor (20).